Embodiments of the inventive concepts generally relate to semiconductor memory devices, and more particularly, to semiconductor memory devices in which two or memory chips are vertically stacked.
The stacking of memory chips within a semiconductor memory device package has been the subject of recent study in an effort to increase memory capacity while maintaining a relative small package foot-print. Herein, these types of devices are referred to as stacked semiconductor memory devices.
Interlayer connection units, such as “through silicon vias” (TSV) are utilized to transmit control and data signals to stacked memory chips of a stacked semiconductor memory device. As a result, signal timing transmission delays can result, for example, between a memory chips receiving signals by way of a TSV and a memory chip receiving signals directly from an external signal terminal. These delays, which can be difficult to precisely measure, may adversely impact the performance of the staked semiconductor memory device.